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"TE Team-Fly® AM FL Y Vector Game Math Processors James Leiterman Wordware Publishing, Inc. Library of Congress Cataloging-in-Publication Data Leiterman, James. Vector game math processors / by James Leiterman. p. cm. Includes bibliographical references and index. ISBN 1-55622-921-6 1. Vector processing (Computer science). 2. Computer games--Programming. 3. Supercomputers--Programming. 4. Computer science--Mathematics. 5. Algorithms. I. Title. QA76.5 .L446 2002 004'.35--dc21 2002014988 CIP © 2003, Wordware Publishing, Inc. All Rights Reserved 2320 Los Rios Boulevard Plano, Texas 75074 No part of this book may be reproduced in any form or by any means without permission in writing from Wordware Publishing, Inc. Printed in the United States of America ISBN 1-55622-921-6 10 9 8 7 6 5 4 3 2 1 0211 Product names mentioned are used for identification purposes only and may be trademarks of their respective companies. All inquiries for volume purchases of this book should be addressed to Wordware Publishing, Inc., at the above address. Telephone inquiries may be made by calling: (972) 423-0090 Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Chapter 1 Introduction . . . . . . . . . . . . . . . . 1 Book Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Graphics 101 . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Algebraic Laws . . . . . . . . . . . . . . . . . . . . . . . . . 11 I-VU-Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Insight. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 2 Coding Standards . . . . . Constants. . . . . . . . . . . . . . . . . . . . . Data Alignment . . . . . . . . . . . . . . . . . Pancake Memory LIFO Queue. . . . . . . . Stack . . . . . . . . . . . . . . . . . . . . . Assertions . . . . . . . . . . . . . . . . . . . . Memory Systems . . . . . . . . . . . . . . . . RamTest Memory Alignment Test . . . . . . Memory Header . . . . . . . . . . . . . . . Allocate Memory (Malloc Wrapper). . . . . Release Memory (Free Wrapper) . . . . . . Allocate Memory . . . . . . . . . . . . . . . Allocate (Cleared) Memory . . . . . . . . . Free Memory — Pointer is Set to NULL . . Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 . 15 . 15 . 18 . 18 . 21 . 24 . 25 . 26 . 27 . 28 . 29 . 29 . 29 . 30 . 31 . 31 . 33 . 36 . 38 . 43 . 43 . 44 . 47 . 51 . 52 . 54 Chapter 3 Processor Differential Insight . Floating-Point 101 . . . . . . . . . . . . . . . . . . Floating-Point Comparison . . . . . . . . . . . . . Processor Data Type Encoding . . . . . . . . . . . X86 and IBM Personal Computer . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . Destination and Source Orientations. . . . . . . Big and Little Endian. . . . . . . . . . . . . . . MIPS Multimedia Instructions (MMI). . . . . . PS2 VU Coprocessor Instruction Supposition. . Gekko Supposition . . . . . . . . . . . . . . . . Function Wrappers. . . . . . . . . . . . . . . . . . iii iv Contents Integer Function Wrappers . . . . . . . . . . . . . Single-Precision Function Quad Vector Wrappers Double-Precision Function Quad Vector Wrappers Single-Precision Function Vector Wrappers . . . . Double-Precision Function Vector Wrappers . . . Exercises . . . . . . . . . . . . . . . . . . . . . . . . Chapter 4 Vector Methodologies Target Processor . . . . . . . . . . . . . Type of Data . . . . . . . . . . . . . . . AoS . . . . . . . . . . . . . . . . . . SoA . . . . . . . . . . . . . . . . . . A Possible Solution? . . . . . . . . . Packed and Parallel and Pickled . . . Discrete or Parallel? . . . . . . . . . . . Algorithmic Breakdown . . . . . . . . . Array Summation. . . . . . . . . . . Thinking Out of the Box (Hexagon) . . Vertical Interpolation with Rounding Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 62 67 68 71 72 .. .. .. .. .. .. .. .. .. .. .. .. .. . 74 . 74 . 75 . 75 . 76 . 77 . 81 . 83 . 86 . 86 . 90 . 91 . 94 Chapter 5 Vector Data Conversion . . . . . . . . . 95 (Un)aligned Memory Access . . . . . . . . . . . . . . . . . . . 95 Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . . . . 95 Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . . . . . 98 Pseudo Vec (AltiVec) . . . . . . . . . . . . . . . . . . . . . . 99 Pseudo Vec (MIPS-MMI) . . . . . . . . . . . . . . . . . . . 99 Pseudo Vec (MIPS-VU0) . . . . . . . . . . . . . . . . . . . 101 Data Interlacing, Exchanging, Unpacking, and Merging . . . . 101 Swizzle, Shuffle, and Splat. . . . . . . . . . . . . . . . . . . . 114 Vector Splat Immediate Signed Byte (16x8-bit) . . . . . . . 114 Vector Splat Byte (16x8-bit) . . . . . . . . . . . . . . . . . 114 Vector Splat Immediate Signed Half-Word (8x16-bit) . . . . 115 Vector Splat Half-Word (8x16-bit) . . . . . . . . . . . . . . 115 Parallel Copy Half-Word (8x16-bit) . . . . . . . . . . . . . 115 Extract Word into Integer Register (4x16-bit) to (1x16) . . . 116 Insert Word from Integer Register (1x16) to (4x16-bit) . . . 116 Shuffle-Packed Words (4x16-bit). . . . . . . . . . . . . . . 117 Shuffle-Packed Low Words (4x16-bit) . . . . . . . . . . . . 117 Shuffle-Packed High Words (4x16-bit). . . . . . . . . . . . 117 Vector Splat Immediate Signed Word (8x16-bit). . . . . . . 118 Vector Splat Word (8x16-bit) . . . . . . . . . . . . . . . . . 118 Shuffle-Packed Double Words (4x32-bit) . . . . . . . . . . 118 Graphics Processor Unit (GPU) Swizzle . . . . . . . . . . . 119 Data Bit Expansion — RGB 5:5:5 to RGB32 . . . . . . . . . . 120 Vector Unpack Low Pixel16 (4x16-bit) to (4x32) . . . . . . 120 Vector Unpack High Pixel16 (4x16-bit) to (4x32) . . . . . . 120 Contents v Parallel Extend from 5 Bits . . . . . . . . . . . . . . . Data Bit Expansion. . . . . . . . . . . . . . . . . . . . . Vector Unpack Low-Signed Byte (8x8) to (8x16-bit) . Vector Unpack High-Signed Byte (8x8) to (8x16-bit) . Vector Unpack Low-Signed Half-Word (4x16) to (4x32-bit) . . . . . . . . . . . . . . . . . . . . . . Vector Unpack High-Signed Half-Word (4x16) to (4x32-bit) . . . . . . . . . . . . . . . . . . . . . . . Data Bit Reduction — RGB32 to RGB 5:5:5 . . . . . . . Vector Pack 32-bit Pixel to 5:5:5 . . . . . . . . . . . . Parallel Pack to 5 Bits. . . . . . . . . . . . . . . . . . Data Bit Reduction (with Saturation) . . . . . . . . . . . Vector Pack Signed Half-Word Signed Saturate . . . . Vector Pack Signed Half-Word Unsigned Saturate . . Vector Pack Unsigned Half-Word Unsigned Saturate . Vector Pack Unsigned Half-Word Unsigned Modulo . Vector Pack Signed Word Signed Saturate . . . . . . . Vector Pack Signed Word Unsigned Saturate . . . . . Vector Pack Unsigned Word Unsigned Saturate . . . . Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 6 Bit Mangling . . . . . . . Boolean Logical AND . . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . Boolean Logical OR . . . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . Boolean Logical XOR (Exclusive OR) . . . . Pseudo Vec . . . . . . . . . . . . . . . . . Toolbox Snippet — The Butterfly Switch . I-VU-Q . . . . . . . . . . . . . . . . . . . Boolean Logical ANDC . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . Boolean Logical NOR (NOT OR) . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . Graphics 101 — Blit . . . . . . . . . . . . . . Copy Blit . . . . . . . . . . . . . . . . . . Transparent Blit . . . . . . . . . . . . . . . Graphics 101 — Blit (MMX) . . . . . . . . . Graphics Engine — Sprite Layered . . . . Graphics Engine — Sprite Overlay. . . . . Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 121 122 122 . . . 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 123 124 124 125 125 125 126 126 127 127 128 128 . 129 . . 130 . . 131 . . 132 . . 134 . . 136 . . 138 . . 139 . . 139 . . 140 . . 142 . . 144 . . 147 . . 148 . . 149 . . 149 . . 150 . . 151 . . 151 . . 152 . . 152 . . 153 . . 153 . . 154 . . 155 vi Contents Chapter 7 Bit Wrangling. . . Parallel Shift (Logical) Left . . . . . Pseudo Vec . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . Pseudo Vec (MMI) . . . . . . . . Parallel Shift (Logical) Right . . . . Pseudo Vec . . . . . . . . . . . . Parallel Shift (Arithmetic) Right. . . Pseudo Vec . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . Pseudo Vec (MIPS) . . . . . . . . Rotate Left (or N-Right) . . . . . . . Pseudo Vec . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . Pseudo Vec (MIPS) . . . . . . . . Secure Hash Algorithm (SHA-1) . . Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 . . 158 . . 159 . . 162 . . 163 . . 165 . . 168 . . 169 . . 170 . . 172 . . 175 . . 176 . . 176 . . 179 . . 180 . . 181 . . 182 . . 184 . . 187 . . 191 . 192 . . 193 . . 194 . . 195 . . 196 . . 196 . . 197 . . 197 . . 198 . . 198 . . 201 . . 204 . . 205 . . 206 . . 207 . . 207 . . 208 . . 209 . . 210 . . 213 . . 214 . . 215 . . 215 . . 217 . . 218 Chapter 8 Vector Addition and Subtraction . . Vector Floating-Point Addition . . . . . . . . . . . . . . Vector Floating-Point Addition with Scalar . . . . . . . . Vector Floating-Point Subtraction . . . . . . . . . . . . . vmp_VecNeg . . . . . . . . . . . . . . . . . . . . . . Vector Floating-Point Subtraction with Scalar . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . Vector Floating-Point Reverse Subtraction . . . . . . . . Vector Addition and Subtraction (Single-Precision) . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . Vector Scalar Addition and Subtraction . . . . . . . . . . Single-Precision Quad Vector Float Scalar Addition . Single-Precision Quad Vector Float Scalar Subtraction Vector Integer Addition . . . . . . . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . Vector Integer Addition with Saturation. . . . . . . . . . Vector Integer Subtraction . . . . . . . . . . . . . . . . . Vector Integer Subtraction with Saturation . . . . . . . . Vector Addition and Subtraction (Fixed Point) . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . Contents vii Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . . . . 218 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Chapter 9 Vector Multiplication and Division . Floating-Point Multiplication . . . . . . . . . . . . . . . NxSP-FP Multiplication . . . . . . . . . . . . . . . . (Semi-Vector) DP-FP Multiplication . . . . . . . . . . SP-FP Scalar Multiplication . . . . . . . . . . . . . . DP-FP Scalar Multiplication . . . . . . . . . . . . . . NxSP-FP Multiplication — Add . . . . . . . . . . . . SP-FP Multiplication — Subtract with Rounding . . . Vector (Float) Multiplication — Add . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . Vector Scalar Multiplication . . . . . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . Graphics 101 . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . Graphics 101 . . . . . . . . . . . . . . . . . . . . . . Vector Floating-Point Division . . . . . . . . . . . . . . (Vector) SP-FP Division . . . . . . . . . . . . . . . . (Semi-Vector) DP-FP Division . . . . . . . . . . . . . SP-FP Scalar Division . . . . . . . . . . . . . . . . . DP-FP Scalar Division . . . . . . . . . . . . . . . . . SP-FP Reciprocal (14 bit). . . . . . . . . . . . . . . . SP-FP Reciprocal (2 Stage) (24 Bit) . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . Packed {8/16/32} Bit Integer Multiplication . . . . . . . 8x8-bit Multiply Even . . . . . . . . . . . . . . . . . 8x8-bit Multiply Odd . . . . . . . . . . . . . . . . . . 4x16-bit Multiply Even . . . . . . . . . . . . . . . . . 4x16-bit Multiply Odd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 . . 222 . . 222 . . 222 . . 223 . . 223 . . 223 . . 224 . . 224 . . 224 . . 225 . . 228 . . 229 . . 230 . . 231 . . 231 . . 232 . . 233 . . 233 . . 234 . . 236 . . 237 . . 238 . . 238 . . 242 . . 243 . . 243 . . 243 . . 244 . . 244 . . 245 . . 246 . . 246 . . 247 . . 247 . . 249 . . 249 . . 250 . . 250 . . 251 . . 251 . . 252 viii Contents 8x16-bit Parallel Multiply Half-Word . . . . . . . . . . . Nx16-Bit Parallel Multiplication (Lower) . . . . . . . . . Nx16-bit Parallel Multiplication (Upper) . . . . . . . . . Signed 4x16-bit Multiplication with Rounding (Upper) . . Unsigned Nx32-bit Multiply Even . . . . . . . . . . . . . Integer Multiplication and Addition/ Subtraction . . . . . . . Signed Nx16-bit Parallel Multiplication and Addition . . Signed Nx16-bit Parallel Multiplication and Subtraction . [Un]signed 8x16-bit Multiplication then Add . . . . . . . Signed 8x16-bit Multiply then Add with Saturation . . . . Signed 8x16-bit Multiply Round then Add with Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . Integer Multiplication and Summation-Addition . . . . . . . 16x8-bit Multiply then Quad 32-bit Sum. . . . . . . . . . 8x16-bit Multiply then Quad 32-bit Sum. . . . . . . . . . 8x16-bit Multiply then Quad 32-bit Sum with Saturation . Vector (Integer) Multiplication and Add . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . . . . Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 10 Special Functions . Min — Minimum. . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . Max — Maximum . . . . . . . . . . NxSP-FP Maximum. . . . . . . . 1xSP-FP Scalar Maximum . . . . 1xDP-FP Scalar Maximum . . . . Nx8-bit Integer Maximum . . . . Nx16-bit Integer Maximum. . . . 4x32-bit Integer Maximum . . . . Vector Min and Max . . . . . . . Pseudo Vec . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . Pseudo Vec (MIPS) . . . . . . . . CMP — Packed Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 253 254 255 255 256 257 257 258 259 259 260 260 260 261 261 262 263 265 266 267 268 269 270 271 273 273 274 . 275 . . 275 . . 275 . . 278 . . 279 . . 279 . . 279 . . 280 . . 280 . . 281 . . 281 . . 281 . . 282 . . 283 . . 283 . . 284 Contents ix Packed Compare if Equal to (=) . . . . . . . . . . . Packed Compare if Greater Than or Equal (³ ) . . . . Packed Compare if Greater Than (>) . . . . . . . . . Absolute . . . . . . . . . . . . . . . . . . . . . . . . . Packed N-bit Absolute . . . . . . . . . . . . . . . . Averages . . . . . . . . . . . . . . . . . . . . . . . . . Nx8-bit [Un]signed Integer Average . . . . . . . . . Nx16-bit [Un]signed Integer Average . . . . . . . . 4x32-bit [Un]signed Integer Average. . . . . . . . . Sum of Absolute Differences . . . . . . . . . . . . . . 8x8-bit Sum of Absolute Differences . . . . . . . . 16x8-bit Sum of Absolute Differences . . . . . . . . SQRT — Square Root . . . . . . . . . . . . . . . . . . 1xSP-FP Scalar Square Root . . . . . . . . . . . . . 4xSP-FP Square Root . . . . . . . . . . . . . . . . . 1xDP-FP Scalar Square Root . . . . . . . . . . . . . 2xDP-FP Square Root. . . . . . . . . . . . . . . . . 1xSP-FP Scalar Reciprocal Square Root (15 Bit) . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . SP-FP Square Root (2-stage) (24 Bit) . . . . . . . . 4xSP-FP Reciprocal Square Root (Estimate) . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . Vector Square Root . . . . . . . . . . . . . . . . . . Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . Pseudo Vec (MIPS) . . . . . . . . . . . . . . . . . . Graphics 101 . . . . . . . . . . . . . . . . . . . . . . . Vector Magnitude (Alias: 3D Pythagorean Theorem) Pseudo Vec . . . . . . . . . . . . . . . . . . . . . . Pseudo Vec (X86) . . . . . . . . . . . . . . . . . . . Pseudo Vec (PowerPC) . . . . . . . . . . . . . . . . Graphics 10..."

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